1. Field of the Invention
The present invention relates to a frequency divider circuit, and more particularly to a frequency divider circuit capable of operating at high frequencies.
2. Description of the Related Art
Known frequency divider circuits operate in a master-slave flip-flop configuration of interconnected first and second sections which receive a clock signal having a frequency as an input and which output a signal having a frequency value substantially half of the clock frequency. The master-slave operation of such known circuits is achieved through feedback of the output signal of one circuit block as an additional input signal to the other circuit block and vice versa, i.e. as an input signal other than the clock signal.
A known frequency divider circuit 5 is shown in FIG. 1 and includes a first circuit section 10 and a second circuit section 20. (Connections between the two circuit portions 10 and 20 are omitted for ease of illustration.) Each circuit section has a pair of transistors that are connected to a DC voltage supply V.sub.dd and which receive a clock signal as an input at their gate terminals. For example, section 10 has transistors Q1 and Q2 that receive an input clock signal CLK of a frequency f, and section 20 has a pair of transistors Q3 and Q4 that receive as inputs at their gate terminals the complement of the clock signal CLK' having the frequency f. Circuit 5 generates output signals A, B and their logic complements A' and B' at frequencies substantially half the frequency of the clock signal, i.e. f/2, and the output signals are also used as input signals. In other words, the output signals are fed back to circuit sections 10 and 20 such that output signals B and B' generated by section 20 are received as inputs to section 10, and output signals A and A' are received as inputs to section 20. Each circuit section has two pairs of parallel input transistors, shown as transistor pairs Q5, Q5' and Q6 and Q6' for section 10, and Q7, Q7' and Q8, Q8' for section 20. Each transistor in each pair has a gate terminal that receives one of the generated output signals or its complement (A or A', B or B'). The circuit 5 operates as a sample and hold circuit wherein when, for example, section 10 samples, section 20 holds its then-present output signal state. In particular, when the clock signal CLK goes high, e.g., to a value equivalent to a logic "1", circuit section 10 performs a sampling function and circuit section 20 performs a hold function. When clock signal CLK goes low, e.g., to a value equivalent to a logic "0", CLK' goes high and circuit section 20 performs a sampling function while circuit section 10 performs a hold function wherein it maintains its prior output signal value.
The problem with circuit 5 is that the speed of operation is limited and, thus, the circuit outputs cannot adequately track or be generated in real time at high clock frequencies. For example, for 0.25 .mu.m CMOS devices operating from a 2v Vdd supply, the maximum operating frequency is approximately 3 GHz. Two primary factors affect the operating speed of circuit 5. The first is the inherent RC time constant of each circuit section. The capacitance "C" in the RC time constant is the result of parasitic capacitance of the transistors in each circuit section, which is an inherent property of the transistors resulting from their manufacture and operating conditions. The resistance ("R") value is either the "on" or "off" impedance values of the transistors Q1, Q2, Q3 and Q4. Thus, when Q1 and Q2 are off, such as when signal CLK is high (Q1 and Q2 are shown by way of example as PMOS devices), which occurs precisely when circuit section 10 is in sampling mode, there is a high impedance which yields a high RC time constant and, consequently, a slow transition time and an increased delay in effecting a change in value of the output signals.
Another problem resulting in operating frequency limitations is the dependency of the change of state of each transistor pair (Q5 and Q5', Q6 and Q6', Q7 and Q7', Q8 and Q8') on the differential value of the input signals, i.e. the difference in values between signals A and A' for section 20 and the difference in signal values between signals B and B' for section 10. For the output signals (A, A', B, B') of each circuit section to change rapidly, a large differential signal is required so that, for example, when signal B is at a low value causing transistor Q6 to turn off, signal B' is at a high value causing transistor Q5 to turn on. However, as signals B and B' are both generated from section 20, and due to the circuit section configuration, these signals are close in value to each other.
For example, when circuit section 20 is in the hold mode, i.e. when signal CLK' is low, transistors Q3 and Q4 are on (for PMOS devices). Assuming signal B is low and signal B' is high, transistor Q7' will be on and transistor Q8' will be off. Thus, as for signal B', this signal is represented by the charge level on the parasitic capacitance at node Y', which is charged by voltage V.sub.dd through transistor Q4. The value of signal B, on the other hand, fluctuates somewhat because it is determined by the charge level on the parasitic capacitance at node Y, which continuously charges through transistor Q3 and continuously discharges through transistor Q7'. This causes the voltage differential between signals B and B' to be decreased, which inhibits the activation of transistors Q5 and Q6 at high speed, thereby delaying the changes of state of signals A and A'. The same result occurs with respect to circuit section 10 when CLK goes high.